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If you've ever sent a board out for fabrication with a 100-ohm differential target and gotten back a report showing 94 ohms, you already know that impedance testing is where design theory meets manufacturing reality. I've spent years cross-sectioning coupons and staring at TDR traces trying to figure out why a "correct" stackup produced an out-of-spec board. This guide covers what actually happens during multilayer PCB impedance testing, how to interpret the results, and where most engineers get tripped up.

What Is Multilayer PCB Impedance Testing?

Multilayer PCB impedance testing is the measurement process used to verify that the manufactured trace impedance matches the designed target, typically within ±10%. The industry standard method is Time Domain Reflectometry (TDR), governed by IPC-TM-650 2.5.5.7. A TDR sends a fast-rise-time pulse (usually under 35 picoseconds) down a test coupon and measures the reflected voltage. Any impedance change along the trace shows up as a bump or dip in the reflection waveform.

This is a manufacturing verification step, not a design step. Design calculators and field solvers predict impedance before fabrication. Testing confirms whether the physical board matches that prediction after etching, lamination, and plating.

Why Test Coupons Instead of the Real Traces?

This is the part most articles skip. You cannot probe a buried stripline trace inside a finished board without destroying it. So fabricators build a test coupon, a small strip of board panel that runs alongside your actual production boards, using the same lamination cycle, same copper weight, same etch batch, and same layer stackup.

The coupon includes access pads sized for TDR probes, usually placed at trace lengths of 3 to 6 inches, long enough for the reflection to stabilize but short enough to fit on the panel border. If your fabricator tests a coupon that wasn't processed in the same panel run as your boards, the numbers are meaningless. This is one detail I always confirm with a supplier before trusting an impedance report.

How to Read a TDR Plot Without Guessing

A TDR plot shows impedance (Y-axis) against distance or time (X-axis). Here's how I interpret one on the shop floor:

Flat, stable line at target impedance: This is what you want. A 50-ohm single-ended trace should show a flat line hovering near 50 ohms for the full probed length.

Rising step near the probe point: Usually indicates connector or via transition capacitance at the launch point. Not a fabrication defect if it settles quickly.

Dip in the middle of the trace: Often caused by a via stub, a necked-down trace section, or a gap in the reference plane directly beneath the trace. This is the single most common defect I've traced back to a design or panel issue, not a process issue.

Gradual drift over trace length: Points to dielectric thickness variation from lamination, often from uneven copper density (a heavy pour on one side pulling prepreg thickness off target during press).

End-of-line spike: Usually just the open-circuit termination reflecting. Ignore it unless it appears mid-trace.

Step-by-Step: How Impedance Testing Actually Runs in Production

1. Coupon design is finalized alongside the stackup. Test points are added per impedance-controlled layer, not just per board.

2. Panels are etched and laminated as one batch, coupons included on the panel border.

3. Coupons are cut from the panel after lamination, before or during the drilling stage depending on process flow.

4. TDR probes contact the coupon pads, and the equipment fires the pulse and records the waveform.

5. Each impedance-controlled layer is measured independently, since a 6-layer board might have both microstrip outer layers and stripline inner layers with different targets.

6. Results are compared against the tolerance band (commonly ±10%, tighter for RF work at ±5%).

7. A signed impedance test report ships with the order, documenting measured values per layer.

If any single layer falls outside tolerance, the batch should be flagged before shipment. This is where fabricator discipline actually matters. A supplier that only tests "on request" or skips documentation on standard orders is asking you to trust a number you can't verify.

Common Mistakes That Waste Engineers' Time and Money

Assuming the calculator value is the final value. Formula-based estimates (like the standard Z0 microstrip equation) are a starting point. Actual laminate Dk varies by ±0.2 to 0.3 across FR-4 batches, which alone can shift impedance 3 to 5%. Only a field solver plus post-fabrication TDR confirms the real number.

Ignoring reference plane continuity under the coupon. A coupon with a split ground plane beneath it will test differently than the actual signal trace if the real board's reference plane is continuous (or vice versa). The coupon layout has to mirror the real trace's environment, not just its width.

Testing only one coupon per panel. Etch factor and dielectric thickness can vary slightly across a large panel. For tight-tolerance jobs, I ask for coupons at multiple panel positions, not just one corner.

Treating out-of-spec results as automatically the fabricator's fault. Sometimes the design itself specified a stackup that was never physically achievable with standard tooling, for example a trace width narrower than the fab's etch resolution allows. A good fabricator will flag this during DFM review before production, not after testing fails.

Impedance Testing Pros and Cons by Method

For the vast majority of multilayer boards running USB, PCIe, DDR, or Ethernet interfaces, standard TDR coupon testing per IPC-TM-650 2.5.5.7 is sufficient and expected.

Frequently Asked Questions

What impedance tolerance should I expect from a multilayer PCB? Plus or minus 10% is the standard manufacturing tolerance. A 100-ohm differential target is generally accepted between 90 and 110 ohms.

Does every layer need separate impedance testing? Yes, if every layer carries a controlled-impedance interface with a different stackup geometry. A microstrip outer layer and a stripline inner layer will not share the same test result even on the same board.

Can I request impedance testing on a prototype run? Yes, and you should. Testing at prototype stage catches stackup or material issues before you commit to volume tooling and larger panel quantities.

Why did my board pass simulation but fail TDR testing? The most frequent cause is a difference between the assumed Dk in your simulation and the actual laminate batch's measured Dk, combined with etch undercut that wasn't fully compensated in the artwork.

Where This Matters When Choosing a Fabrication Partner

Impedance testing is only as trustworthy as the fabricator running it. What I look for is a supplier that documents test coupon results per layer as standard practice, not an add-on, and that uses laminates with known, stable Dk values across batches, such as Shengyi or Kingboard materials, rather than unspecified generic stock.

I've worked with PCBgogo on multilayer boards up to 40 layers where impedance-controlled stackups needed tight coordination between material selection and lamination process. Their in-house factory model means the same team handling stackup planning also runs the lamination and TDR verification, without handing the board off between separate subcontractors. For prototype iterations where a stackup needs a quick re-test after a design tweak, their 24-hour expedite option has been useful for keeping a project moving without waiting on a full standard cycle. When a report shows an unexpected number, having responsive engineering support to walk through the coupon data directly, rather than a generic ticket queue, saves real time.

Final Takeaway

Multilayer PCB impedance testing is not a formality tacked onto the end of fabrication. It's the only step that confirms your design math survived contact with real copper, real dielectric, and a real lamination press. Know how your coupon was built, know how to read the TDR plot yourself, and work with a fabricator that treats per-layer documentation as standard, not optional.